1. Field of the Invention
The present invention relates to microprocessor caches in computer systems, and more specifically to a method for determining cacheable address and write protect memory address regions in a computer system using a preset memory address value and a programmable single ended limit register to provide the respective memory address boundaries for each respective memory address region.
2. Description of the Prior Art
The personal computer industry is a vibrant and growing field that continues to evolve as new innovations occur. The driving force behind this innovation has been the increasing demand for faster and more powerful computers. A major bottleneck in personal computer speed has historically been the speed with which data can be accessed from memory, referred to as the memory access time. The microprocessor, with its relatively fast processor cycle times, has generally had to wait during memory accesses to account for the relatively slow memory access times. Therefore, improvement in memory access times has been one of the major areas of research in enhancing computer performance.
In order to bridge the gap between fast processor cycle times and slow memory access times, cache memory was developed. A cache is a small amount of very fast, expensive, zero wait state memory that is used to store a copy of frequently accessed code and data from system memory. The microprocessor can operate out of this very fast memory and thereby reduce the number of wait states that must be interposed during memory accesses. When the processor requests data from memory and the data resides in the cache, then a cache read hit occurs, and the data from the memory access can be returned to the processor from the cache without incurring wait states. If the data is not in the cache, then a cache read miss occurs, and the memory request is forwarded to the system memory. The data is then retrieved from system memory as would normally be done if the cache did not exist.
The management or control of a cache is generally performed by a device referred to as a cache controller. The cache controller is principally responsible for keeping track of the contents of the cache as well as controlling data movement into and out of the cache. One responsibility of the cache controller is the preservation of cache coherency, which refers to the requirement that the copy of main memory held in the cache be identical to the data held in main memory. The cache controller is also generally responsible for the determination of which main memory addresses are capable of residing in the cache, referred to as cacheable addresses.
Microprocessor caches are generally able to cache most of the memory addresses in main memory. However, some memory addresses are defined as non-cacheable, or incapable of residing in the cache, because of cache coherency reasons. One example of memory that is generally designated as non-cacheable is memory that is dual ported or capable of being accessed by different ports. Dual ported memory is generally defined as being non-cacheable because of the cache coherency problems that are associated with this type of memory. The cache coherency problem arises because the cache controller is unable to snoop the memory access by a local master because the local master accesses the memory location from a different port than would the processor, and the cache controller does not have access to this port for snooping purposes. An example of dual ported memory that exists in personal computer systems is the memory located on a local area network (LAN) card. The LAN card memory is accessible by both the microprocessor and the cache controller via one port located on one side of the LAN memory and by a local processor on the LAN card via a different port located on the other side of the LAN memory. Cache coherency problems arise because the cache controller is unable to snoop local processor accesses to the LAN memory. Other examples of non-cacheable memory are memory that is mapped for input/output (I/O) devices and also bank switched or expanded memory.
The cache controller is generally charged with the duty of determining which main memory addresses are designated as cacheable and which main memory addresses are designated as non-cacheable. Conventionally, this has been done with a fixed address decode using programmable array logic (PAL) devices. A variation is to place a random access memory (RAM) on the address lines, with the data in the RAM being the cacheable status of the address block. Another variation is to use a series of pairs of limit registers which define the boundaries of cacheable and non-cacheable address regions. Each pair of limit registers stores memory address values that define the upper and lower boundaries of the address region. A comparator is generally associated with each stored memory address value to determine if the memory address generated by the computer system is between the respective upper or lower boundary address values defining a memory address region. If the generated memory address resides between the upper and lower address boundaries defining the address region, then the generated memory address is deemed cacheable or non-cacheable depending on the function of the respective limit registers.
This method of cacheable address determination generally includes a large amount of logic circuitry because two limit registers for storing of the upper and lower address boundaries and a comparator for each limit register are required for each cacheable or non-cacheable address region, and there are generally several such regions in the memory space of a computer system. The large amount of logic circuitry required for each respective cacheable address region limits the number of cacheable address regions that can be provided in the memory space of the computer system, thereby limiting the amount of cacheable main memory and consequently reducing the effectiveness of the cache memory.
Some background on the memory organization of personal computers compatible with those previously manufactured and sold by International Business Machines Corporation (IBM) is deemed appropriate. IBM's first personal computer, the IBM PC, included 20 address lines and therefore could only address one Mbyte of memory space. This one Mbyte memory space was located between memory address 00000H and memory address FFFFFH and was divided as follows. The lower 640 kbytes were designated for user memory, which was generally reserved for the operating system, a user's programs and associated data. The next 128 kbytes of memory was set aside for use by the video section of the computer system to store the video data that is displayed on the video monitor and the video ROM routines that are required for the operation of the video monitor. The video ROM routines comprise a set of programs that provide essential support for the operation of the video section, and these programs act as an interface between application software written for the computer system and the video hardware, which operates to display desired images on the video monitor.
The next 192 kbytes of memory after the video display memory area were originally referred to as the option ROM space. This memory area originally had no real assignment, but has been used for a variety of purposes that have arisen in the evolving history of IBM-compatible computers. The last 64 Kbytes in the 1 Mbyte memory space of the original IBM PC was used to hold the computer's built in system ROM programs. The system ROM holds a key set of programs that provide essential support for the operation of the computer, including the POST programs that make sure the computer is in good working order at power on and the routines referred to as the basic input-output system or BIOS. The BIOS programs provide detailed and intimate control of the various parts of the computer, particularly the input/output (I/O) peripherals, and in general act as an interface between the computer's hardware and the software written for the computer.
One of the uses that has been found for the 192 kbyte option ROM area discussed above has been as a growth area for the system ROM routines, which originally occupied only the last 64 Kbytes of the one Mbyte address space. When new equipment or devices are added to the computer which require built-in software support, the additional system ROM programs required for these new devices are generally located in the option ROM area. Another use for the option ROM area has been for extra video display memory or video RAM that is required by video display adapter cards based on new video standards. Additionally, many new functions or options have been developed which need RAM and ROM space, and this RAM and ROM is generally located in this area.
The IBM PC family has been developed around a family of microprocessors manufactured by Intel Corporation (Intel), referred to as the 8088 family of microprocessors. The original members of the IBM PC family were limited to addressing only one Mbyte of memory due to the fundamental design of the 8088 microprocessor on which they were based, which included only 20 address lines. Intel later introduced the 80286 microprocessor, which included 24 address lines and could directly address up to 16 Mbytes of physical memory. The addition of the 80286 microprocessor to a computer system allows for a logical address space of 16 Mbytes. However, the original design of the IBM PC and its DOS operating system were limited to the use of the original one Mbyte of memory, and they were generally unable to use the additional address space provided by the 80286 microprocessor.
In order to take advantage of the additional memory space provided by the 80286 microprocessor, IBM-compatible computer systems have developed what is called extended memory, which is the memory address space above the original one Mbyte address space located from memory address 100000H on up. The amount of extended memory available in a computer system generally depends on the amount of physical memory resident in the computer system greater than the original one Mbyte of memory discussed above. This additional memory can generally reside anywhere in the processor's logical address space between memory address 100000H and memory address FFFFFFH, which is the 16 Mbyte limit associated with the 80286 microprocessor. In order for an application program to take advantage of some of this special extended memory, the program used some of the services provided by the computer's system ROM programs. One of these system ROM services transferred blocks of data in whatever size needed between the special extended memory and the conventional one Mbyte memory.
Another feature that is generally included in IBM-compatible personal computers is a ROM relocation feature. The system ROM and video ROM memory which reside in the one conventional Mbyte memory address space discussed above are generally much slower than the high-speed RAM which comprises the remainder of system memory. Therefore, in order to improve system performance during execution of the BIOS routines which reside in the system ROM and video ROM, many computer systems include a ROM relocation feature which allows the system ROM and/or video ROM to be relocated or copied to high-speed RAM. In computer systems using the 80286 microprocessor, the ROM is generally copied to the upper 128 kbyte RAM memory area just below 16 Mbytes, which is reserved for this purpose. When so copied, this 128 kbyte RAM location, referred to as shadow RAM, becomes dual mapped or accessible to two sets of logical addresses: its original RAM memory addresses and the ROM memory addresses of the ROM memory that has been relocated to this location.
The shadow RAM can be designated as write protected to ensure that the data cannot accidentally change and effectively remains a ROM. The shadow RAM may also be designated as cacheable memory to further improve system performance during execution of the system ROM routines. If the shadow RAM is designated as cacheable memory, it is also generally designated as write-protected inside the cache controller to ensure that ROM memory data which is placed in the cache retains its read-only status inside the cache. The cache controller therefore generally requires a means to determine whether a memory address generated by the computer system has been designated as write protected. This has generally been accomplished in the same manner as has the determination of cacheable address regions in the cache. The standard method was a fixed mapping, and as an alternative, two registers can be associated with a write protect memory address region to define the respective upper and lower memory address boundaries of the write protect region.
The system ROM includes a series of test and initializations programs referred to as the Power-On Self-Test (POST), which the computer performs at power on to ensure that the computer is in good working order. When the computer is reset or turned on, the microprocessor is directed to a reset vector location in high memory at memory address FFFFF0H to retrieve the correct memory location at which to begin the POST. Memory address FFFFF0H is interpreted by the memory controller during a system reset or power on of the computer system to access the ROM location where a power on reset vector is located. The power on reset vector points to the appropriate memory location where the POST programs begin. It is generally desirable that the high memory location where the power on reset vector is addressed be designated non-cacheable in order to prevent the reset vector from being placed in the cache. If the reset vector were located in the cache when a system reset was initiated, the microprocessor would attempt to retrieve the reset vector from the cache and therefore could receive an incorrect vector, resulting in a "crash" of the computer system.